The present invention relates to MOS devices and, more particularly, to a rugged and reliable low voltage dual-well trench MOS device having low on-resistance and improved body diode reverse recovery characteristics.
U.S. Pat. Nos. 4,975,751 and 5,091,336, the disclosures of which are incorporated herein by reference, describe high voltage component devices with low series resistance. However the recent proliferation of battery-powered, portable communication electronics has increased the need for low voltage, low on-resistance power MOSFETs for efficient power management. Furthermore, because such devices are frequently used in applications that involve inductive loads, it is desirable that they have high UIS (Unclamped Inductive Switching) capability. This is an extremely high stress process, during which the amount of avalanche energy absorbed by the device is expected to be as high as possible without resulting in catastrophic device failure. This capability is generally referred to as the device ruggedness. In addition, some applications such as synchronous rectifiers require that the body diode of a power MOSFET have a low reverse recovery charge and soft reverese recovery characteristics.
U.S. Pat. No. 6,137,139, the disclosure of which is incorporated herein by reference, describes a low voltage dual-well MOS device that is rugged and reliable, exhibits low on-resistance, and exhibits improved body diode reverse recovery characteristics.
Unfortunately, items of concern such as device breakdown rating, on-resistance, improved UIS capability, and desirable body diode characteristics are often in conflict with one another. Thus, there is an ongoing need for improved MOS devices that exhibit an optimum combination of these characteristics, a need that is met by the present invention.
The present invention is directed to a rugged, reliable, low-voltage dual-well trench MOS device having low on-resistance, and improved body diode reverse recovery characteristics, and comprising a semiconductor substrate on which is disposed a lightly doped upper layer of a first conduction type. The upper layer includes a doped first well region of the first conduction type and a doped well region of the second conduction type underlying the first well region. The upper layer further includes at its upper surface a heavily doped source region of the first conduction type and a heavily doped body region of a second and opposite conduction type. A trench gate comprising a conductive material separated from the upper layer by an insulating layer is disposed in the upper layer of the substrate.